Different types of memory are used in electronic apparatus for various purposes. Read-only memory (ROM) and random-access memory (RAM) are two such types of memory commonly used within computers for different memory functions. ROM retains its stored data when power is switched off and therefore is often employed to store programs that are needed for powering-up an apparatus. ROM, however, does not accommodate writing. RAM, on the other hand, allows data to be written to or read from selected addresses associated with memory cells and, therefore, is typically used during normal operation of the apparatus.
Two common types of RAM are dynamic RAM (DRAM) and static RAM (SRAM). DRAM is typically used for the main memory of computers or other electronic apparatuses since, though it must be refreshed, it is typically inexpensive and requires less chip space than SRAM. Though more expensive and space-consumptive, SRAM does not require refresh, making it faster. These attributes make SRAM devices particularly desirable for portable equipment, such as laptop computers and personal digital assistants (PDAs).
A typical SRAM device includes an array of addressable memory cells arranged in columns and rows. A typical SRAM cell includes two access transistors and a flip-flop formed with two cross-coupled inverters. Each inverter has a pull-down (driver) and a pull-up (load) transistor. The gates of the access transistors in each row are connected to a word line and the sources of each of the access transistors in each column are connected to either one of a bit line pair, BL or BL_. Peripheral circuitry associated with the rows (or word lines) and peripheral circuitry associated with the columns (or bit lines) facilitate reading data from, and writing data to, the SRAM cells.
Generally, to read data from an SRAM cell, a word line driver activates a word line according to an address decoded by a row decoder and received via a signal path that typically includes an address bus connected to the SRAM device. The access transistors turn on and connect the outputs of the flip-flop to the bit line pair sending signals representing the data in the SRAM cell to a sense amplifier coupled to the bit line pair. The sense amplifier produces a logical 0 or 1 from the potential difference on the bit line pair, which is, in turn, provided to external circuitry of the associated electronic apparatus, perhaps through a buffer.
Two considerations govern SRAM device design with respect the way in which reads are performed. First, the contents of the SRAM cells must survive being read. By virtue of their length, bit lines have significant capacitance and resistance. Charging the bit lines must not overwhelm the small currents and voltages within an SRAM cell that encode its contents. Otherwise, the contents may become corrupt.
Second, the read ought to be performed as quickly as possible to increase the overall speed of the SRAM device. Sense amplifiers increase read speed by detecting bit line voltages more quickly. The bit lines are precharged and equalized to support a faster read without upsetting the SRAM cell.
These two design considerations must be balanced in selecting the correct voltage at which to precharge the bit lines. However, selecting the proper bit line precharge voltage to use with respect to an SRAM device is a matter of tradeoff. The lower that the bit line precharge voltage is, the better that quiescent current (IDDQ) and static noise margin (SNM) characteristics of the SRAM device tend to be.
Notwithstanding this fact, lowering the bit line precharge voltage below a certain point also causes SNM to degrade. Further, the lower that the bit line precharge voltage is, the lower read current (Iread) is, particularly at a low word line driver (metal-oxide semiconductor, or MOS, drain) voltages (Vdd) . Also, with a lower bit line precharge voltage, the gate-source voltage (Vgs) on the p-channel transistors contained in the precharge circuit is reduced, resulting in a longer bit line precharge time.
Accordingly, what is needed in the art is a better way to precharge bit lines. What is also needed in the art is a circuit that yields faster bit line precharging.